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SX1223
SX1223
425 - 475 MHz / 850 - 950 MHz Integrated UHF Transmitter
GENERAL DESCRIPTION
The SX1223 is a single chip transmitter operating in UHF frequency bands including the 434, 869 and 915 MHz license-free ISM (Industrial Scientific and Medical) bands. Its highly integrated architecture allows for minimum external components while maintaining design flexibility. All major RF communication parameters are programmable and most of them can be set dynamically. The SX1223 offers the advantage of high data rate communication at rates of up to 153.6 kbit/s. The SX1223 is optimized for low cost applications while offering high RF output power. The device is suitable for applications which have to satisfy either the European (ETSI-300-220) or the North American (FCC part 15) regulatory standards.
KEY PRODUCT FEATURES
* * * * * * * RF output power: up to +10 dBm Low power consumption: TX = 25.8 mA @ 10 dBm (typical) Supply voltage down to 2.0 V Data rate from 1.2 to 153.6 kbit/s On-chip frequency synthesizer Continuous phase 2-level FSK modulation Very small RoHS green package (TQFN24, 4mm x 4mm)
ORDERING INFORMATION
Part number SX1223I073TRT(1)
(1)
Temperature range -40 to +85 C C
Package TQFN24
APPLICATIONS
* * * Automated Meter Reading (AMR) Home Automation and Access Control High-Quality Speech, Music and Data over RF
TR refers to tape & reel. T refers to Lead Free package. This device is WEEE and RoHS compliant.
Rev 5 May 2007
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SX1223
Table of Contents
1 2 3 3.1 3.2 3.2.1 3.2.2 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.3 4.4 5 5.1 5.2 5.2.1 5.2.2 5.2.3 6 6.1 6.2 6.3 6.4 6.5 7 Functional Block Diagram .................................................................................................................. 3 Pin description..................................................................................................................................... 4 Electrical Characteristics.................................................................................................................... 5 Absolute Maximum Operating Ranges.................................................................................................. 5 Specifications ........................................................................................................................................ 5 Operating Range ................................................................................................................................... 5 Electrical Specifications......................................................................................................................... 5 General description............................................................................................................................. 7 Frequency synthesizer........................................................................................................................... 7 General Structure .................................................................................................................................. 7 Crystal Oscillator ................................................................................................................................... 8 VCO....................................................................................................................................................... 8 Charge Pump ...................................................................................................................................... 10 Loop Filter............................................................................................................................................ 10 Lock Detect.......................................................................................................................................... 11 Modulator............................................................................................................................................. 11 Introduction.......................................................................................................................................... 11 Data Interface ...................................................................................................................................... 11 Bit Rate Setting for MW1 and MW2 .................................................................................................... 12 Deviation Setting for MW1 and MW2 .................................................................................................. 12 Shaping for MW1 and MW2 ................................................................................................................ 13 Modulator Saturation for MW1 and MW2............................................................................................ 13 Summary of Modulator Settings for MW1 and MW2........................................................................... 13 Frequency deviation setting for MW3.................................................................................................. 13 Power Amplifier ................................................................................................................................... 14 Voltage regulators ............................................................................................................................... 14 Serial Interface definition and Principles of operation .................................................................. 15 Serial Control Interface........................................................................................................................ 15 Configuration and Status registers ...................................................................................................... 16 Operating Modes ................................................................................................................................. 16 Other Settings...................................................................................................................................... 17 Optional and Test Parameters ............................................................................................................ 19 Application Information .................................................................................................................... 21 Matching network of the transmitter .................................................................................................... 21 Reference crystal for the frequency synthesizer ................................................................................. 22 Loop filter components ........................................................................................................................ 22 Recommended modulation conditions ................................................................................................ 22 TYPICAL APPLICATION SCHEMATICS ............................................................................................ 23 Packaging information...................................................................................................................... 24
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SX1223
The SX1223 is a single chip transmitter operating in the 433, 868 and 915MHz license free ISM (Industrial Scientific and Medical) frequency bands; the frequency range is selectable between 425-475 MHz and 850-950 MHz. The modulation scheme is 2-FSK. The circuit has 4 functional modes: sleep mode, where all the blocks are switched off, standby mode, where only the crystal oscillator is on, synthesizer mode, where the frequency synthesizer is running, and transmission mode, where all the blocks are on, including the power amplifier. It complies with European (ETSI EN 300-220-1) and North American (FCC part 15) regulations. There are three different methods of modulation: - (mw1) pulling the VCO in closed loop: all the specified bit rates can be implemented, but a DC-free coding scheme is needed (e.g. Manchester), which means that the real information rate is half the bit rate, - (mw2) pulling the VCO in open loop: all the specified bit rates can be implemented, and NRZ coding is allowed; but, since the control voltage of the VCO will drift due to leakage currents, the duration of the transmission is limited, - (mw3) switching between two frequency divider ratios in closed loop; bit rates from 1.2 to 19.2 kbit/s are achievable with this method. The circuit works on two selectable supply voltage ranges: - (sv1) the high range (2.2 V to 3.6 V), where the on-chip regulators are activated, - (sv2) the low range (2.0 V to 2.5 V), where the on-chip regulators are off. A 3-wire bi-directional bus is used to communicate with SX1223 and gives access to the configuration register. An output clock of 1 MHz is user selectable for driving an external micro-controller. SX1223 comes in a RoHS green TQFN-24 package (body size: 4 mm x 4 mm).
1
FUNCTIONAL BLOCK DIAGRAM
CRYSTAL
LOOP FILTER
VDDF
XTA
XTB
LD
CPOUT
VARIN
OSCILLATOR
LOCK DETECT
VDD
SO
LDO CLOCK GEN LDO
M PFD PFD
Open Loop OPAMP
DATA & CONTROL INTERFACE
/
SI EN SCK
VDDP
N,A / N,A
RFOUT
PA
/2 2 /2 2
VCO
VCO
DATAIN DCLK CLKOUT
MOD BIAS LDO
SX1223
VDDD VDD
Figure 1: SX1223 block diagram
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SX1223
2
PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VDD VSSP VDDP RFOUT VSSP PTATBIAS/PAC XTB XTA VDDD VSSD VDD LD CLKOUT DCLK DATAIN SCK EN SI SO CPOUT VARIN VSSF VDDF CIBIAS I/O OUT IN/OUT IN/OUT IN/OUT OUT OUT OUT IN IN IN IN OUT OUT IN OUT Function Main analog power supply Max 3.6V in sv1-mode Max 2.5V in sv2-mode PA ground In sv1-mode: PA LDO output, capacitor needed In sv2-mode: PA power supply, max 2.5 V RF output PA ground PTAT source bias resistor / PA start-up control capacitor Crystal oscillator pin & input for external reference Crystal oscillator pin In sv1-mode: Digital LDO output, capacitor needed In sv2-mode: Digital power supply, max 2.5V Digital ground Main digital power supply Max 3.6V in sv1-mode Max 2.5V in sv2-mode Lock detect output Output clock (1 MHz) Data clock output Data input 3-wire interface clock input Enable signal for the 3-wire interface 3-wire interface data input 3-wire interface data output PLL charge pump output VCO varactor input Analog ground In sv1-mode: Analog LDO output, capacitor needed In sv2-mode: Analog power supply max 2.5 V CI source bias resistor
Note: Thermal Pad on the bottom of the package must be connected to ground.
Thermal Pad
24 1
bottom view
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SX1223
3
ELECTRICAL CHARACTERISTICS
3.1 ABSOLUTE MAXIMUM OPERATING RANGES Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol VDDmax Tmax Description Supply voltage Storage temperature Min. -0.4 -55 Max. 3.9 125 Unit V C
The device is ESD sensitive and should be handled with precaution. 3.2 3.2.1 SPECIFICATIONS Operating Range Description Supply voltage (*) Temperature Load capacitance on digital ports Min. 2.0 -40 Max. 3.6 85 25 Unit V C pF
Symbol VDD T CLop
(*) Divided in two ranges: - (sv1) high range, 2.2 V - 3.6 V, using on-chip regulators, - (sv2) low range, 2.0 V - 2.5 V, without using the regulators. 3.2.2 Electrical Specifications
The table below gives the electrical specifications of the transmitter under the following conditions: Supply Voltage = 3.3 V, temperature = 25 2-leve l FSK, fc = 915 MHz, Output power = 10 dBm, Bit rate = 38.4 C, kb/s, f = 100 kHz, XTAL = 16 MHz, modulation by pulling the VCO in open loop (mw2), and conditions as defined in section 6, unless otherwise specified. Symbol IDDSL IDDST IDDFS IDDT FR FDA FDA_L FDA BR BR_3 SPICLK
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Description Supply current in sleep mode Supply current in standby mode Supply current in FS mode Supply current during transmission Frequency range Frequency deviation Frequency deviation Variation of frequency deviation Bit rate Bit rate for mw3 mode SPI clock frequency (SCK)
Conditions
Min -
Typ 0.3 0.2 5 25.8 14 -
Max 1 0.3 6 475 950 255 200 + 15 153.6 19.2 1
Unit A mA mA mA mA MHz MHz kHz kHz % kbit/s kbit/s MHz
Crystal oscillator running, CLKOUT off Frequency synthesizer running 10 dBm 0dBm
425 850
For FR from 850 to 950 MHz For FR from 425 to 475 MHz
5 5 - 15
Modulation modes mw1 mw2 Modulation mode mw3 SCK duty cycle 50% +/-10%
1.2 1.2
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SX1223
Symbol HRFOP SRFOP XTAL TS_OS TS_OS_QS Description Highest RF output power RF output power steps Crystal oscillator frequency Oscillator wake-up time Oscillator wake-up time in quick start-up mode Conditions Highest programmable output power RF output power step size (8 steps available) Recommended value: 16 MHz From sleep mode Quick start-up mode IDDST_QS_typ=0.9mA (XCO_quick_start, XCO_high_I = 10) From standby mode (oscillator running) frequency at most 5 kHz away from the target TS_TR TD_TX Transmitter wake-up time Transmission duration in mw2 mode From FS mode (frequency synthesizer running) Duration during which the output signal is a proper FSK signal and the carrier frequency doesn't drift by more than 50 kHz from the time when the transmitter has reached its steady-state (including PA) Same conditions as TD_TX, but over the whole temperature range At 10 dBm output power, modulated signal Measured on a 150 kHz bandwidth centered at 150 kHz from the carrier, f = 40 kHz At 10 dBm output power, modulated signal Measured on a 250 kHz bandwidth centered at 250 kHz from the carrier, f = 60 kHz At 10 dBm output power, unmodulated signal Measured at 50 kHz from the carrier in mw3 mode On pin CLKOUT % VDD % VDD 30 500 s ms 2 ms 0.8 0.15 40 2 MHz ms ms Min 8 Typ 10 3 Max Unit dBm dB
TS_FS
Frequency synthesizer wake-up time
TD_TXW
Transmission duration in mw2 mode Power transmitted in the 150 kHz adjacent channel
15
-
-
ms
ACP
-
-16
dBm
ACP_mw3
Power transmitted in the 250 kHz adjacent channel in mw3 modulation mode
-
-23
-17
dBm
PHN
Phase noise of the output signal
-
-83
-80
dBc/Hz
CLKOUT VIH VIL
Output clock Digital input level high Digital input level low
75 -
1 -
25
MHz % %
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SX1223
4
GENERAL DESCRIPTION
The SX1223 is a 2-level FSK transmitter. The circuit operates in one of two frequency ranges, 425 to 475 MHz, and 850 to 950 MHz, allowing the 3 main ISM frequency bands (434 MHz, 869 MHz and 915 MHz) to be addressed by the circuit. It is capable of operating at data rates between 1.2 and 153.6 kbit/s, making it ideally suited for applications where high data rates are required. The SX1223 is a highly programmable device - channel, bit rate, frequency deviation and output power - which makes it extremely flexible to meet a large number of end user requirements. The main functional blocks of the SX1223 are the frequency synthesizer, the modulator, the power amplifier (PA), the voltage regulators and some additional service blocks. The device also includes a set of configuration registers and a digital interface. In a typical application, the SX1223 is programmed by a microcontroller via the 3-wire serial bus SI, SO, SCK to write to and read from the internal registers. The Frequency Synthesizer generates the carrier (the local oscillator (LO) signal). The Modulator performs the modulation of the carrier by the input bit stream. The Power Amplifier amplifies the modulated RF signal to the antenna port. The Voltage Regulators generate regulated supply voltages for the different parts of the chip, and allow battery voltages up to 3.6 V to be used. The Service Blocks provide the internal voltage and current sources and provide all the necessary functions for the circuit to work properly. The Configuration Registers are a set of registers that are used to store various settings to operate the SX1223 transmitter circuit. Please refer to Section 5.2 for the detailed descriptions of these registers. These registers are accessed in write or read mode through the 3-wire serial bus, as described in Section 5.1. The Digital Interface provides internal control signals for the whole circuit according to the configuration register settings.
4.1
FREQUENCY SYNTHESIZER
4.1.1 General Structure The frequency synthesizer is an integer-N PLL and consists of a voltage-controlled oscillator (VCO), a crystal oscillator, a prescaler, programmable frequency dividers and a phase-detector. The loop-filter is external for flexibility and can be a simple passive circuit. The lengths of the M and N and A counters are respectively 12, 12 and 6 bits. To enable the prescaler Prescal_s register (address 16, bit 4) has to be written to 1. The M, N and A values can be calculated from the formula:
f RF = f XCO (16 N + A) M ( 2 - FreqBand )
where fXCO: fRF: FreqBand:
Crystal oscillator frequency RF frequency 0: RF frequency 425-475 MHz 1: RF frequency 850-950 MHz
M is the divide factor applied to the reference frequency, N and A are the counters of the frequency divider in the feedback loop of the PLL. There are two sets of each of these divide factors (M0, N0, A0 and M1, N1, A1). In modulation modes mw1 and mw2 (register bit Modulation1=0), only the M0, N0 and A0 are used to fix the carrier frequency. If modulation by using the dividers is selected (mw3, Modulation1=1, Modulation0=0), the two sets are used to program the two RF
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SX1223
frequencies corresponding to the transmission of the two possible values `0' and `1'; these frequencies are then separated by twice the specified single sided frequency deviation f. 4.1.2 Crystal Oscillator The crystal oscillator (XCO) provides the PLL with the reference signal. The schematic of the crystal oscillator's external components for 16 MHz is shown in Figure 2.
XTB, pin 7
XTA, pin 8
5p6
5p6
Figure 2: External crystal oscillator circuit with additional (optional) external capacitances
The crystal should be connected between pins XTA and XTB (pin 8 and 7). Either internal or external loading capacitors for the crystal can be used. Internal capacitors can be enabled by setting the XCOcap_en bit to 1. Faster start-up time is expected when using external capacitors. The total capacitance when XCOcap_en=1 (and no external capacitors) is 9 pF. Using a crystal with a load capacitance of 9 pF will give the expected oscillation frequency. If XCOcap_en=0, the loading capacitors can be calculated by the following formula:
CL =
1 1 1 + C1 C2
+ C parasitic
The parasitic capacitance is the pin input capacitance and PCB stray capacitance. For instance, for a 9pF load crystal and a total parasitic capacitance of 6 pF the recommended values of the external load capacitors are 5.6 pF. If an external reference is going to be used instead of a crystal, the signal shall be applied to pin 7, XTB. Due to internal biasing, AC coupling is recommended for use between the external reference and the XTB pin. The start-up time of the crystal oscillator can vary from 150us to 800us depending on the settings shown in Table 15. Therefore, to save current consumption, the XCO should be turned on before any other circuit block. During start-up the XCO amplitude will eventually reach a sufficient level to trigger the M-counter. After counting 2 Mcounter output pulses the rest of the circuit is enabled. Two bits are available to speed up the crystal oscillator start-up: XCO_high_I increases the bias current and XCO_quick_start boosts this current but only at the start; the first output pulse from the M-divider turns this boost current off. Typical values for XCO start-up time and current consumption are tablulated below: XCO_quick_start, XCO_high_I IDDST [uA] TS_OS [us] 00 200 800 01 250 750 10 900 200 11 950 150
Table 1: Oscillator start-up time
A reference clock can be generated by SX1223 for use by an external microcontroller. The ClkOut_en configuration bit determines the status of the CLKOUT pin. When set high CLKOUT is enabled, otherwise it's disabled. When enabled, the output frequency at CLKOUT is the crystal oscillator frequency divided by 16, and is then 1 MHz for a crystal at 16 MHz. This clock signal is disabled in Sleep Mode. When disabled, the CLKOUT pin is set to ground. 4.1.3 VCO The VCO is fully integrated and has no external components. It oscillates at 1.8 GHz and is divided by 2 or 4 in the 900 MHz or the 450 MHz band respectively (FreqBand = 1 or 0). Additionally two bits in the configuration registers set the VCO frequency and three bits control the bias current. The two VCO_freq bits have to be programmed by
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SX1223
the user according to the selected frequency band, whereas the three VCO_IB bits can be either forced by the user or set automatically by the circuit which will select the combination having the best phase noise. This automatic setting can be enabled by setting the three VCO_IB bits to `0'. Table 2 lists the bias setting used for the different VCO_freq settings in automatic mode. When any of the VCO_IB bit is set to 1, it will overrule the automatic setting. RF frequency 425/850 MHz 434/868 MHz 457/915 MHz 475/950 MHz
VCO_IB2 1 1 0 0
VCO_IB1 1 0 1 0
VCO_IB0 VCO_freq1 VCO_freq0 1 0 0 1 0 1 1 1 0 0 1 1
Table 2: VCO bit settings.
The bias bits optimize the phase noise, and the frequency bits control a capacitor bank in the VCO. The tuning range, the RF frequency versus varactor voltage, is dependent on the VCO frequency setting, and is shown in Figure 3. When the tuning voltage is in the range from 1 to 1.6V, the VCO gain is at its maximum, approximately 6570 MHz/V. It is then recommended that the varactor voltage is kept as much as possible in this range.
VCO gain Vdd=3.3V, LDO_en=1, VCO_IB=0
Freq [MHz] 1040 1020 1000 980 960 940 920 900 880 860 840 820 800 0 0.5 1 1.5 2 2.5 Vvaractor [V]
VCO_freq=11 VCO_freq=10 VCO_freq=01 VCO_freq=00
Figure 3: RF frequency vs. varactor voltage and VCO frequency bit
The input capacitance at the varactor pin must be taken into considerations when designing the PLL loop filter. This can be critical when designing a loop filter with high bandwidth, which gives relatively small component values. The input capacitance is approximately 6 pF. For test purposes, the VCO can be bypassed by applying a differential local oscillator (LO) signal to the device on pin CPOUT and VARIN. A resistor of 18 k to ground and a series capacitor of 47 pF are needed on both pins for proper biasing. The register bit VCO_by must be set to `1'.
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SX1223
4.1.4 Charge Pump
The charge pump current can be set to either 125 or 500 A by the CP_HI bit. The default value at power-up is 125 A (CP_HI = `0'). The choice of this current affects the loop filter component values (see section 4.1.5). For most applications the lowest current mode is recommended. For those applications using a high phase detector frequency and a high PLL bandwidth, 500 A may provide a better solution.
4.1.5 Loop Filter The design of the PLL filter will strongly affect the performance of the frequency synthesizer. The PLL filter is kept external for flexibility. The parameters to be considered when designing the loop filter for the SX1223 are primarily the modulation mode and bit rate. These will also affect the switching time and phase noise. The frequency modulation can be done in three different ways with the SX1223, either by closed-, open loop VCO modulation or by modulation with the internal dividers, see Table 3 and modulation selection guide in Table 35. Modulation1 Modulation0 0 0 0 1 1 0 1 1 State Closed loop VCO-modulation (mw1) Open loop VCO-modulation (mw2) Modulation by A,M and N (mw3) Not used
Table 3: Modulation modes
Comments VCO is phase-locked VCO is free-running Modulation inside PLL
R1 C2 20
C3
R1 C2 20
C1
C3
PCB SX1223
R1 C2 20 C1 R2
C3
PCB SX1223
XCO /M PFD
21
PCB SX1223
XCO
VCO
21
21
/M PFD VCO
XCO
/M PFD VCO
OL opamp
MOD / N,A /2
MOD / N,A /2
MOD / N,A /2
Modulation mw1
Modulation mw2
Modulation mw3
Figure 4: Modulation modes
In closed loop VCO modulation (mw1), the PLL bandwidth needs to be sufficiently low ( Bit Rate / 20), so as to prevent the VCO tracking the modulation and cancelling the modulation. Using the dividers in mw3 mode, the PLL needs to lock on a new carrier frequency for every new data bit. Now the PLL bandwidth needs to be sufficiently high ( Bit Rate / 2). It may be necessary to implement a third order filter to futher suppress the phase detector frequency spurs, For the open loop VCO modulation case (mw2), the PLL bandwidth can be large, as the PLL is deactivated during the transmission burst and there is no requirement to supress the phase detector frequency To increase the transmission time in the open loop case, a capacitor of 47 nF can be connected on pin VARIN to ground (NPO type is advised if the transmission duration is critical). The internal opamp must be enabled to drive this capacitor, by setting the bit OL_opamp_en to 1. A schematic for a third order loop filter is shown in Figure 5a. For a second order filter, C3 is not connected and R2 is set to 0 . When designing a third order loop filter, the internal capacitance on the VARIN pin of approximately 6 pF must be taken into consideration. Figure 5b shows the loop filter configuration for the open loop VCO modulation case.
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SX1223
R2
CPO pin 20 UT,
VARIN, pin 21
CPO pin 20 UT,
VARIN, pin 21
C1
C2
C3
C1
C2 47nF C3
R1
R1
a)
b)
Figure 5:
Loop filter for a) closed loop modulation and b) open loop modulation
4.1.6 Lock Detect A lock detector can be enabled by setting LD_en=1. When enabled pin LD is set high, indicating that the PLL is in lock. The lock detect signal can also be used to control the PA; if LD is low the PA is turned off and vice versa. To enable this function, the PA_LDc_en must be set to `1' (see section 4.3). Care must be taken when monitoring the LD during data transmission using the closed loop modulation. The LD may show that the PLL is not locked, especially when the loop filter bandwidth is too high relative to the bit rate. 4.2 MODULATOR
4.2.1 Introduction The modulator has a high degree of flexibility, and there are thus several values that need programming. First, the settings concerning the data bit rate must be determined, then these values will be used in the calculation of the frequency deviation. Finally the user must check that the modulator won't saturate with the values chosen. 4.2.2 Data Interface The "data interface" can be programmed to synchronous or asynchronous mode (see Table 4). Sync_en 0 1 State DataClk pin off DataClk pin on. Comments Transparent transmission of data Bit-clock is generated by transmitter
Table 4: Synchronizer mode
In asynchronous mode only the DATAIN pin is used for transmitting the data to the SX1223. In synchronous mode the SX1223 is defined as "Master" and provides a data clock on pin DCLK that allows the user to utilize low cost micro controller reference frequency. The data interface is defined in such a way that all user actions should take place on falling edges of DCLK as illustrated in Figure 6. The data are sampled by the SX1223 on the rising edges of DCLK.
DATAIN DCLK
Figure 6:
Time diagram of the data interface in synchronous mode
Before entering into transmit mode (mw1 or mw2), it is important to set DATAIN to high impedance. The data is provided directly to the modulation circuit and violation of this may cause abnormal behavior.
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SX1223
4.2.3 Bit Rate Setting for MW1 and MW2 The bit rate is set by first dividing the crystal oscillator frequency by an integer in the range [1..63] in a programmable divider, then this frequency is divided further by powers of two. The equation describing the bit rate as a function of RefClk_K and BRn is
BR = Re fClk _ K 23+ BRn f XTAL
(4.1)
where: fXTAL: RefClk_K: BRn:
Crystal oscillator frequency. Integer in the range [1..63] (6 bit). Integer in the range [0..5] (3 bit).
A procedure to determine the settings for the desired bit rate is described below: 1. Set BRn to 0. 2. Calculate RefClk_K by using this formula: Re fClk _ K =
BR 23+ BRn f XTAL
.
3. If RefClk_K is too high, increment n by one, and repeat step 2, above In some cases several combinations of RefClk_K and BRn will provide the required bit rate. In these cases BRn should be chosen with the following in mind: A lower BRn offers better waveform shaping or spectral efficiency, but may cause modulator saturation at some bit rates. 4.2.4 Deviation Setting for MW1 and MW2 Frequency deviation is controlled by user parameters RefClk_K, MOD_I, and MOD_A together with physical parameters fXTAL and KVCO. All user parameters can be set in software, and fXTAL (crystal oscillator frequency) is set when designing in the radio chip. KVCO (VCO gain) is a parameter of the radio chip, and is not controllable by the user. The crystal oscillator frequency, fXTAL, is divided by RefClk_K to generate the modulator clock. Since this modulator clock is controlling the rise and fall times for the modulator, the frequency deviation is inversely proportional to this clock. The relationship is shown in equation (4.2).
f DEV Re fClk _ K f XTAL
(4.2)
It is assumed that K will be constant for most applications to keep bit-rate and shaping constant, although this is not a requirement. The control parameters of the frequency deviation are MOD_I and MOD_A. Of these two, MOD_I is the parameter that controls the signal generation, while MOD_A controls attenuation of this signal. The reason for using an attenuator is to be able to generate small deviations at high values of RefClk_K. The relationship is shown in equation (4.3).
f DEV
MOD _ I 2 MOD _ A
(4.3)
Finally, the VCO gain is given by equation (4.4).
KVCO = Const1 + (Const 2 f C (2 - FreqBand )) 2 - FreqBand
(4.4)
where: Const1: Const2: fC: FreqBand:
- 30.6324 x 109 54.7
Carrier frequency. Frequency band. 0: 400MHz and 1: 900MHz.
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From equation (4.4), it can be seen that VCO is proportional to carrier frequency. MOD_I is the best parameter to alter to counteract this effect if necessary. Combining equations (4.2), (4.3), and (4.4) gives an expression for the frequency deviation:
f = RefClk_K MOD _ I Const1 + (Const 2 f C (2 - FreqBand )) f XTAL 2 - FreqBand 2 MOD _ A
(4.5)
4.2.5 Shaping for MW1 and MW2 The modulation waveform will be shaped due to the charging and discharging of a capacitor. The waveform looks like a Gaussian filtered signal with a BandwidthPeriod-product (BT) given by:
BT = 2 BRn
It can be seen from this equation that a low BRn gives a low shaping factor.
(4.6)
In addition to this, it is possible to smooth the modulator output in a programmable low-pass filter. This filter is controlled by the parameter MOD_F. The parameter should be set according to equation (4.7).
MOD _ F
150 x 103 BR
(4.7)
4.2.6 Modulator Saturation for MW1 and MW2 The modulator output voltage is generated with a capacitor that is being charged. This means that there is a risk of saturating the modulator if the charge received by the capacitor is too large. The maximum value of MOD_I can be determined by using equation (4.8).
f XTAL -6 MOD _ I Re fClk _ K 28 x 10 + 1
(4.8)
If it turns out that the MOD_I-range is too small for the application, the solution can be found by increasing BRn and decreasing RefClk_K accordingly. 4.2.7 Summary of Modulator Settings for MW1 and MW2 The necessary equations needed for the use of the modulator are (4.1), (4.5), (4.6), (4.7), and (4.8). The table below gives a summary of the meaning of the parameters. Symbol RefClk_K BRn MOD_F MOD_I MOD_A Range (inclusive) 1..63 0..5 0..3 1..31 0..4 Explanation The crystal oscillator frequency is divided by this number to produce the modulator clock, and it is divided further down by 8 to produce bit rate clock. Number of extra divide-by-two for the bit rate clock. Programmable smoothing filter after attenuator. This can be programmed in four steps, and will produce reasonable results for the highest bit rates. Frequency deviation. The deviation is linearly dependent on this variable. Frequency deviation attenuator (or range selector). The attenuations are (values 0 through 4, respectively)
1 , 1 , 1 , 1 , and 1 . 1 248 16
Table 5: Modulator settings
4.2.8 Frequency deviation setting for MW3 In MW3 the modulation is done by switching between two frequency divider ratio sets: M0, N0, A0 and M1, N1, A1. The frequency f0 will be generated using the first set and frequency f1 using the second set, corresponding to the transmission of the two possible values `0' and `1'.
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SX1223
The single sided frequency deviation f is half of the difference between f0 and f1. Bit rates from 1.2 to 19.2 kbit/s are achievable with this method. 4.3 POWER AMPLIFIER The output power of the PA is programmable in 8 steps, with approximately 3 dB between each step. This is controlled by bits PA2 to PA0 according to Table 6 below. PA2..PA0 = 111 provides the maximum output power of typically 10 dBm. PA2
0 0 0 0 1 1 1 1
PA1
0 0 1 1 0 0 1 1
PA0
0 1 0 1 0 1 0 1
Output power
21dB attenuation 18dB attenuation 15dB attenuation 12dB attenuation 9dB attenuation 6dB attenuation 3dB attenuation Maximum power
Table 6: PA power settings
The PA is normally controlled by the two Mode bits (off for all cases other than Mode1, Mode0 = `11'). The PA can in addition be controlled by the lock detector, if the bit PALDc_en is set high (and LD_en='1'). In this case, once LD goes high after entering the transmit mode, the PA is turned on and will remain on until a new event changing the working mode occurs (such as a new configuration transmitted through the 3-wire interface). During open loop VCO modulation, mw2, the PLL is deactivated during the transmission time. After an open loop transmission, the frequency may have drifted off, and it is therefore important that the PA is turned off before the PLL is activated. The PA behaves this way as long as PALDc_en=1. After a transmission burst, DATAIN must be set to high impedance, the PA is turned off and the PLL is reactivated. Once LD goes high again, the PA is turned on and a new burst of data can be transmitted. To reduce the harmonics for passing the ETSI and FCC regulations a 3rd order LC-filter (T or configuration) should be implemented between the output of the PA and the antenna port. The ramp-up of the PA is achieved using an internal capacitor (approx. 29pF). If this is not sufficient to pass relevant regulations, bit PAC_en can be enabled and an external capacitor connected to pin 6. Using PA_IB3,2 and PAB_IB3,2 bits the reference current can be selected to bias the PA and the PA buffer as shown in Table 31. An 82k resistor should be connected between pin 24 and ground for the CI bias. If the option PTAT bias source with external resistor is chosen, an 18k resistor should be connected between pin 6 and ground. This option can not be used when PAC_en option is selected. In this case the resistor is replaced by a capacitor, and the functionality changes as described above. 4.4 VOLTAGE REGULATORS The SX1223 has three internal Low Dropout Regulators (LDOs) powering up different parts of the circuit, as can be seen from the block diagram (Figure 1). The LDOs can be turned off (default setting is on) by setting the LDO_en='0'. When LDO_en='1', the power supply range is 2.2 - 3.6 V (sv1). Power must be applied to pins 1 and 11. A good quality factor capacitor is needed on each of the LDO output for stability (pins 3, 9 and 23). In sleep mode all the LDOs are turned off. The interface and control blocks run on unregulated power, and the register contents will be stored and hence the device can be programmed whilst in this mode. When LDO_en=0, the power supply range is 2.0 - 2.5 V (sv2). Power must be applied to pin 1, 3, 9, 11 and 23. In this case capacitors are only needed for normal noise decoupling.
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SX1223
5
SERIAL INTERFACE DEFINITION AND PRINCIPLES OF OPERATION
5.1 SERIAL CONTROL INTERFACE A 3-wire bi-directional bus (SCK, SI, SO) is used to communicate with SX1223 and gives access to the configuration register. SCK and SI are input signals supplied externally, for example by the microcontroller. The SX1223 configures the SO signal as an output pin during read operation, and it is tri-stated in other modes. The falling edge of the SCK signal is used to sample the SI pin to write data into the internal shift register of the SX1223. The rising edge of the SCK signal is used to output data by the SX1223 to the SO pin, so the microcontroller should sample data at the falling edge of SCK. Be aware that reading data on SO output is forbidden whilst in transmit mode. The signal EN must be low during the whole write and read sequences. In write mode the actual content of the configuration register is updated at the rising edge of the EN signal. Before this, the new data is stored in temporary registers whose content does not affect the transceiver settings. The timing diagram of a write sequence is given in Figure 7 below. The sequence is initiated when a Start condition is detected, that is when the SI signal is set to "0" during a period of SCK. The next bit is a read/write (R/W) bit which should be "0" to indicate a write operation. The next 5 bits are the address of the control register A[4:0] to be accessed, MSB first. Then, the next 8 bits are the data to be written in the register. The data on SI should change at the rising edges of SCK, and is sampled at the falling edge of SCK. The SI line should be at "1" for at least one clock cycle on SCK before a new write or read sequence can start. In doing this, users can do multiple registers write without a rising EN signal in between. The duty cycle of SCK must be between 40% and 60% and the maximum frequency of this signal is 1 MHz. Over the operating supply and temperature range, set-up and hold time for SI on the falling edge of SCK are 200ns.
SCK
SI
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
EN
SO
HZ
Figure 7: Write sequence into configuration register
The time diagram of a read sequence is given in figure below. The sequence is initiated when a Start condition is detected, that is when the SI signal is set to "0" during a period of SCK. The next bit is a read/write (R/W) bit which should be "1" to indicate a read operation. The next 5 bits are the address of the control register A[4:0] to be accessed, MSB first. Then the data from the register are transmitted on the SO pin. The data become valid at the rising edges of SCK and should be sampled at the falling edge of SCK. After this, the data transfer is terminated. The SI line must stay high for at least one clock cycle on SCK to start a new write or read sequence. The typical current drive on SO is 2mA @ 2.7V, the maximum load is CLop. When the serial interface is not used for read or write operations, both SCK and SI should be set to "1". Except in read mode, SO is set to "HZ".
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SX1223
Figure 8: Read sequence of configuration register.
5.2 CONFIGURATION AND STATUS REGISTERS The SX1223 has several operating modes and configuration parameters which can be programmed by the user. These modes and parameters are stored in a set of internal configuration registers that can be accessed by the microcontroller through the 3-wire serial interface. The detailed contents of the configuration registers are given in the next table. The value attached to each parameter is the default value at power-up. All the undefined bits in the table below should be kept to 0.
Address A[6:0] 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 Default Value D[7:0] Hex 0x3F 0x7D 0x02 0x4B 0x0C 0x1A 0x02 0x00 0x76 0x00 0x22 0x02 0x00 0x76 0x00 0x22 0x20 0xDD
-
Data D7
Modulation [1:0] VCO_IB [2:0] PA_IB [3:0]
D6
Mode [1:0]
D5
Freq_Band PAC_en Mod_I [4:0]
D4
XCOcap_en XCO_Quick_ Start BRn [2:0]
D3
PA [2:0] LDO_en XCO_High_ Current
D2
OL_opamp_ en CP_HI
D1
ClkOut_en PA_LDc_en
D0
Sync_en LD_en
VCO_freq [1:0] Mod_A [2:0] Mod_F [2:0]
RefClk_K [5:0] A0 [5:0] N0 [7:0] M0 [7:0] A1 [5:0] N1 [7:0] M1 [7:0] Prescal_s VCO_by PAB_IB [3:0] M1 [11:8] N1 [11:8] M0 [11:8] N0 [11.8]
Table 7: Contents of the configuration registers and their values at power-on
5.2.1 Operating Modes The SX1223 can be programmed into four different modes by the Mode1 and Mode0 bits, as illustrated in Table 8. Add Bits 0 6-5 Mode1 0 0 1 1 Mode0 0 1 0 1 Mode Sleep mode Standby mode Synthesizer mode Transmit mode Description All blocks off, Register configuration kept (default) Crystal oscillator enabled Crystal oscillator, Frequency synthesizer enabled Crystal oscillator, Frequency synthesizer, PA enabled
Table 8: SX1223 Operating Modes
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SX1223
5.2.2 Other Settings The tables below give the definition of all the parameters of the configuration registers besides the working modes. Add Bits 0 4-2 PA2 0 0 0 0 1 1 1 1 PA1 0 0 1 1 0 0 1 1 PA0 0 1 0 1 0 1 0 1 State 21dB attenuation 18dB attenuation 15dB attenuation 12dB attenuation 9dB attenuation 6dB attenuation 3dB attenuation Max output (default)
Table 9: Power amplifier output power
Add 0
Bit ClkOut_en 1 0 1
State ClkOut off ClkOut on
Comments Output is 0 volt on pin CLKOUT. A clock at XCO frequency divided by 16 is available on pin CLKOUT. (default)
Table 10: Output clock
Add 0
Bit 0
Sync_en 0 1
State DCLK pin off DCLK pin on
Comments Transparent transmission of data Bit-clock is generated by transceiver (default)
Table 11: Synchronizer mode
Add 1
Bit Modulation1 Modulation0 State 7-6 Closed loop VCO-modulation (mw1) 0 0 0 1 1 1 0 1 Open loop VCO-modulation (mw2) Modulation by M, N and A (mw3) Not used
Table 12: Modulation mode
Comments VCO is phase-locked VCO is free-running (default) Modulation inside PLL
Add 1
Bit 5
FreqBand 0 1
Comments RF frequency 425-475 MHz RF frequency 850-950 MHz (default)
Table 13: Frequency band
Add 1
Bit 4
XCOcap_en 0 1
Comments Internal capacitors for the crystal oscillator turned off Internal capacitors for the crystal oscillator turned on, external capacitors not needed (default)
Table 14: XCO internal capacitor
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SX1223
Add 2
Bit XCO_quick_start XCO_high_current 4-3 0 0 0 1 1 0 1 1
Comments Normal XCO bias current (default) Higher XCO bias current Quick start of XCO with normal bias current in steady state Quick start of XCO with higher bias current in steady state
Table 15: XCO start-up control
Add 1
Bit 3
LDO_en 0 1
Comments LDO turned off, min/max VDD is 2.0/2.5 V LDO turned on, min/max VDD is 2.2/3.6 V (default)
Table 16: Low DropOut voltage regulator on/off
Add 1
Bit OL_opamp_en State 2 0 Open loop opamp off Open loop opamp on (default) 1
Comments When opamp is enabled, a capacitor can be added to the varactor pin that will increase the transmission time in open loop modulation (mw2)
Table 17: Open loop opamp on/off
Add 2
Bit 5
PA_C 0 1
Comments Startup time of PA controlled by internal capacitor; PTAT source using the resistor connected to pin6 can be used (default) Startup time of PA controlled by external capacitor connected to pin 6; PTAT source using the resistor connected to pin6 is not available
Table 18: PA start-up control
Add 1
Bit 1
PALDc_en Comments PA is only controlled by Mode1 and Mode0: PA on in transmit mode 0 (Mode1=Mode0=1) (default) 1 In transmit mode, PA is turned on/off by Lock Detect (i.e. LD=1 -> PA on)
Table 19: Lock Detect controlled PA
Add 1
Bit 0
LD_en 0 1
State LD off LD on
Comments Output is low A high indicate a PLL lock (default)
Table 20: Lock Detector
Add 2
Bit 2
CP_HI 0 1
Comments PLL charge pump current is 125 A (default) PLL charge pump current is 500 A
Table 21: Charge pump current
Add Bits VCO_freq1 VCO_freq0 Comments (*) 2 1-0 0 0 Setting for 850 MHz 0 1 Setting for 868 MHz 1 0 Setting for 915 MHz (default) 1 1 Setting for 950 MHz (*) Assuming FreqBand=1. When FreqBand=0, the RF frequency is halved.
Table 22: VCO frequency
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SX1223
Add Bits 3 7-3 MOD_I 1..31 Comments The deviation frequency is linearly dependent of MOD_I
Table 23: Modulator current setting for frequency deviation
Add Bits 3 2-0
MOD_A 0..4
Comments Frequency deviation attenuator (or range selector). The attenuations are (values 0 through 4, respectively)
1 , 1 , 1 , 1 , and 1 . 1 248 16
Table 24: Modulator attenuator setting for frequency deviation
Add Bits 4 5-3
BRn 0..5
Comments The bit rate clock is set by dividing the crystal oscillator frequency by RefClk_K*2^(3+BRn)
Table 25: Bit Rate setting
Add Bits 4 2-0
MOD_F 0..3
Comments Programmable smoothing filter after attenuator. This can be programmed in four steps, and will produce reasonable results for the highest bit rates.
Table 26: Modulator filter setting
Add Bits 5 5-0
RefClk_K Comments The crystal oscillator is divided by this number to produce modulator clock and 1..63 it is divided further down by 2^(3+BRn) to produce the bit rate clock.
Table 27: Modulator and Bit Rate clock setting
Add 16
Bit 4
Prescal_s 0 1
State (default) Prescaler enabled
Comments Reserved.
f RF f XCO = (16 N + A) M ( 2 - FreqBand )
Table 28: Prescaler enable bit
"1" should be written in Prescal_s register to operate SX1223 PLL dividers. 5.2.3 Optional and Test Parameters In most applications, the user has only to be concerned with the parameters given in sections 5.2.1 and 5.2.2. However some options and test modes are available for special purposes. They are described in the tables below. Add Bits 16 7-5 VCO_IB2 1 1 0 0 VCO_IB1 1 0 1 0 VCO_IB0 1 1 1 0 Comments - default = [0 0 1] Bias setting for 850 MHz Bias setting for 868 MHz Bias setting for 915 MHz Bias setting for 950 MHz
Table 29: VCO bias
The two VCO_freq bits have to be programmed by the user according to the selected frequency band, whereas the three VCO_IB bits can be either forced by the user or set automatically by the circuit which will select the combination having the best phase noise. This automatic setting can be enabled by setting the three VCO_IB bits to `0'.
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SX1223
Add 16
Bit 3
VCO_by 0 1
State VCO is active (default) VCO is bypassed
Comment When VCO is bypassed, a differential signal can be applied to the circuit using pin CPOUT and VARIN
Table 30: VCO bypass bit
Add Bits PA_IB3 PA_IB2 17 7-6 0 0 0 1 1 0 1 1 Add Bits PA_IB1 PA_IB0 17 5-4 0 0 0 1 1 0 1 1 Add Bits PAB_IB3 PAB_IB2 17 3-2 0 0 0 1 1 0 1 1 Add Bits PAB_IB1 PAB_IB0 17 1-0 0 0 0 1 1 0 1 1
State PA uses bias current from PTAT bias source, external resistor (Pin 6) PA uses bias current from CI bias source, external resistor (Pin 24) PA uses bias current from internal bias source, PTAT PA uses bias current from internal bias source, PTAT + CI (default) State PA bias current setting, lowest bias current PA bias current setting (default) PA bias current setting PA bias current setting, highest bias current State PAbuffer uses bias current from PTAT bias source, external resistor (Pin 6) PAbuffer uses bias current from CI bias source, external resistor (Pin 24) PAbuffer uses bias current from internal bias source, PTAT PAbuffer uses bias current from internal bias source, PTAT + CI (default) State PAbuffer bias current setting, lowest bias current PAbuffer bias current setting (default) PAbuffer bias current setting PAbuffer bias current setting, highest bias current
Table 31: PA and PAbuffer bias current setting
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SX1223
6
APPLICATION INFORMATION
This section provides details of the recommended components values for the frequency dependant blocks of the SX1223. Note that these values are dependent upon circuit layout and PCB structure.
6.1 MATCHING NETWORK OF THE TRANSMITTER The optimum load impedances for 10 dBm output power at the three main frequencies are given in the following table. 434 MHz PA optimum load 19.4-j2.6 869 MHz 23.5-j1 915 MHz 23.5+j8
Table 32: Optimum load impedances for 10 dBm output power
The schematic of the recommended matching network at the output of the transmitter is given in Figure 9 on the next page.
CT2
SX1223
CT3 LT1
CT4
Figure 9: Transmitter output network
The -section is used to provide harmonic filtering in order to satisfy FCC and ETSI regulations. The typical component values of this matching circuit are given below. Name CT1 CT2 CT3 CT4 LT1 Typical Value for 434 MHz 6.8pF 1pF 10pF 10pF 22nH Typical Value for 869 MHz 6.8 pF NC 15 pF 6.8 pF 4.7 nH Typical Value for 915 MHz 6.8 pF NC 33 pF 4.7 pF 4.7 nH Tolerance 5% 5% 5% 5% 5%
Table 33: Typical component values for the recommended matching network at the output of the transmitter
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SX1223
6.2 REFERENCE CRYSTAL FOR THE FREQUENCY SYNTHESIZER The crystal for the reference oscillator of the frequency synthesizer should have the following typical characteristics: Name Fs CL Rm Cm C0 Description Nominal frequency Load capacitance for fs (on-chip) Motional resistance Motional capacitance Shunt capacitance Min. value Table 34: Crystal characteristics
Typ. value 16.0 MHz (fundamental) 9 pF -
Max. value 40 30 fF 7 pF
6.3 LOOP FILTER COMPONENTS The loop filter component values used in MW2 mode for specification validation are presented below; (see fig.5b) R1 12k 6.4 C1 470pF C2 4.7nF C3 33nF
RECOMMENDED MODULATION CONDITIONS Bit rate [kb/s] 1.2 2.4 4.8 9.6 19.2 32.8 38.4 76.8 153.6 Frequency deviation [kHz] 5 to 255 5 to 255 5 to 255 10 to 255 20 to 255 40 to 255 100 to 255 40 to 255 100 to 255 80 to 255 100 to 255 200 to 255 100 to 255 mw1 mw2 mw1 mw2 mw1 mw2 mw1 mw2 100 kHz 100 kHz 100 kHz 100 kHz 100 kHz 100 kHz 100 kHz 100 kHz Manchester NRZ Manchester NRZ Manchester NRZ Manchester NRZ Continuous Burst (1 kbits for f 100 kHz) Continuous Burst (1 kbits for f 100 kHz) Continuous Burst (2 kbits for f 100 kHz) Continuous Burst (4 kbits for f 100 kHz) Modulation type mw3 Max. carrier frequency step Up to 300 kHz, not regularly spaced Coding Allowed transmission mode
NRZ
Continuous
Table 35: Modulation Type Selection
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SX1223
6.5 TYPICAL APPLICATION SCHEMATICS
C7 VDD C8 C6 VDD
24 23 22 21 20 19
R2
R1 C9
Slave Out SI /EN
18 17
CIBIAS
VDDF
VSSF
VARIN
CPOUT
SO
1
C5
C4
2 3
VDD VSSP
Slave In /Select SPI
VDDP
4 5
SX1223
TQFN24 4x4
SCK DATAIN DCLK CLKOUT
16 15 14 13
Serial Clock Tx Data Input Tx Data Clock Clock Output PLL Lock Detect
RFOUT VSSP PTAT/PAC
L1
C2
6
VDDD
VSSD
VDD
11
XTA
XTB
NC C3 C1
7
8
9
10
12
LD
VDD C11 C10
Figure 10: Application Schematics
Note: refer to chapter 4.3 for pin 6.
Please contact Semtech for applications schematics and bills of materials for Reference Designs.
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SX1223
7
PACKAGING INFORMATION
SX1223 comes in a 24-pin RoHS green TQFN 4x4 package as shown in Figure 11 below.
Figure 11: Package dimensions
The exposed die pad on the bottom of the chip should be soldered. Please contact Semtech for foot print recommendations and PCB gerber files of Semtech reference designs.
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SX1223
(c) Semtech 2006 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
Contact Information
Semtech Corporation Wireless and Sensing Products Division 200 Flynn Road, Camarillo, CA 93012 Phone (805) 498-2111 Fax : (805) 498-3804
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